![]() Inc (Si2) Silicon Integration Initiative, Cmos 45 nm open cell library, in. Ko, High-speed parallel decimal multiplication with redundant internal encodings. S. Gao, D. Al-Khalili, N. Chabini, An improved bcd adder using 6-lut fpgas, in: 10th IEEE International NEWCAS Conference, pp. Sutter, High-speed fpga 10’s complement adders–subtractors. G. Bioul, M. Vazquez, J.P. Deschamps, G. Sutter, Decimal addition in fpga, in 5th Southern Conference on Programmable Logic, 2009. Renaud-Goud, Optimal algorithms and approximation algorithms for replica placement with distance constraints in tree networks, in 2012 IEEE 26th International Parallel and Distributed Processing Symposium, pp. Mhaidat, Fpga implementation of binary coded decimal digit adders and multipliers, in 2012 8th International Symposium on Mechatronics and its Applications, pp. Wolff, Fast binary/decimal adder/subtractor with a novel correction-free bcd addition, in 2011 18th IEEE International Conference on Electronics, Circuits, and Systems, pp. Moreover, the proposed design consumes 34.28% less power in comparison with existing best known approach at a clock frequency of 200 MHz and a reference voltage of 5 V. Since the proposed circuit is improved in both area and delay parameter, it is 53.06% efficient in terms of area-delay product compared to the best known existing BCD adder, which is surely a significant achievement. The proposed BCD adder provides prominent better performance with 20.0% reduction in area and 41.32% reduction in delay for the post-layout simulation. The proposed BCD adder is coded in VHDL and implemented in a Virtex-6 platform targeting XC6VLX75T Xilinx FPGA with a \(-3\) speed grade by using ISE 13.1. The proposed parallel BCD adder gains a radical achievement compared to the existing best known LUT-based BCD adders. A size-minimal and depth-minimal LUT-based BCD adder circuit construction is the main contribution of this paper. BCD adder is more effective with a lookup table (LUT)-based design, due to field programmable gate array (FPGA) technology’s enumerable benefits and applications. In this paper, a tree-structured parallel BCD addition algorithm is proposed with the reduced time complexity \(O(N(\log _2b) (N-1))\), where N = number of digits and b = number of bits in a digit. The binary-coded decimal (BCD) being the more accurate and human-readable representation with ease of conversion is prevailing in the computing and electronic communication.
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